FIG. 1 shows a conventional output buffer circuit 20. The output buffer circuit 20 may be used in an integrated circuit for supplying a high current to an output load in response to an input logic signal voltage. The output buffer circuit 20 has a P-channel output driver circuit 21 and an N-channel output driver circuit 22. The P-channel output driver circuit 21 has a P-channel input 1 which receives a low voltage if the output buffer circuit 20 is to be driven to output a logic `1` and a high voltage otherwise. The N-channel output driver circuit 22 of the output buffer circuit 20 has an N-channel input 2 which receives a high voltage if the output buffer is to be driven to output a logic `0` and a low voltage otherwise. As is common in the art, the input signals at the P-channel input 1 and N-channel input 2 are controlled so they are not both active at the same time. Thus, it is common to use a logic circuit (not shown) for preventing the P-channel input from receiving a low voltage concurrently with the N-channel input receiving a high voltage. A high impedance output occurs when the P-channel input is high at the same time the N-channel input is low.
The voltage inputted on the P-channel input 1 is inverted by an inverter 3. The voltage outputted by the inverter 3 is inverted again by the inverter 4. The voltage outputted by the inverter 4 is fed to the gate input 6 of a P-MOS transistor 5. The source 7 of the transistor 5 is connected to a positive reference supply voltage Vdd and the drain 8 of the transistor 5 is connected to an output pad 9. ("Reference voltage" as used herein is synonymous with bias voltage, i.e., reference voltage means a voltage for biasing an active element so that it operates at a particular driving point of its output characteristics. Furthermore, "positive reference voltage" refers to a reference voltage which is more positive than a corresponding "negative reference voltage." It is understood that either reference voltage can be greater than, less than or equal to zero volts. Prefereably, the negative reference voltage is ground and the positive reference voltage is greater than zero.) When a low voltage is inputted on the P-channel input 1, the transistor 5 supplies the pad with a high current at a high value of the pad voltage, e.g., 5 volts. When a high voltage is inputted on the P-channel input 1, the transistor 5 conducts little or no current and presents a high impedance.
The voltage inputted on the N-channel input 2 is inverted by an inverter 10. The voltage outputted by the inverter 10 is inverted by the inverter 11. The voltage outputted from the inverter 11 is inputted to a gate 13 of an N-MOS transistor 12. The source 14 of the transistor 12 is connected to a negative reference voltage such as ground. The drain 15 of the transistor 12 is connected to the output pad 9. When a high voltage is inputted on the N-channel input 2, the transistor 12 supplies the output pad with a high current at a low value of the pad voltage, e.g., 0.4 volts. When a low voltage is inputted on the N-channel input 2, the transistor 12 conducts little or no current and presents a high impedance. In reality, while the P-channel current supply transistor 5 supplies a current to the pad 9, the N-channel current supply transistor 12 actually sinks a current from the pad 9. Both the supply of current by the P-channel transistor and the sinking of current by the N-channel transistor are referred to herein as supplying a current. (In other words supplying a current may refer to supplying a positive or negative current.)
There are two inverters (3 and 4) in the P-channel output driver circuit 21 and two inverters (10 and 11) in the N-channel output driver circuit 22 to provide a buffer between the logic circuit which supplies the input signals to the P-channel input 1 and N-channel input 2 and the current supply transistors 5 and 12. Specifically, it should be noted that the inverters 4 and 11 slow the turn on of the supply transistors 5 and 12 so that these transistors turn off faster than they turn on.
It is advantageous to increase the throughput of an integrated circuit which has one or more output buffer circuits. The throughput of an integrated circuit refers to the amount of data that flows through an integrated circuit. The output buffer circuits in an integrated circuit are desirably able to change from outputting a high voltage to a low voltage and vice versa at a high speed. Thus, in the output buffer circuit 20 of FIG. 1, the transistor 5 must shut off quickly and the transistor 12 must turn on quickly, when the input 1 to the P-channel driver circuit 21 changes from low to high and the input 2 to the N-channel driver circuit 22 changes from low to high. Likewise, the transistor 12 must shut off quickly and the transistor 5 must turn on quickly, when the input 2 to the N-channel driver circuit 22 changes from high to low and the input 1 to the P-channel driver circuit 21 changes from high to low. Furthermore, the throughput of an integrated circuit is also increased by increasing the number of bits outputted by the integrated circuit in parallel. Thus, a plurality of output buffer circuits such as shown in FIG. 1 must be provided in parallel for outputting the logic values of a corresponding plurality of bits.
The increasing throughput demands on output buffer circuits present a problem for conventional MOS output buffers. MOS transistors used in such output buffers, such as the transistors 5 and 12 of FIG. 1, primarily operate in the non-saturated region. In the non-saturated region, MOS transistors output a current which is related to their drain-source voltage. In order to sink a high current at 0.4 volts, the transistor 12 must have a large channel conductance. The transistor 12 may sink many times more current (e.g., ten times more) during the abrupt transition of the drain-source voltage from a high voltage of 5 volts to a low voltage of 0.4 volts, than during steady state operation at the low voltage of 0.4 volts. This is because the output pad 9 has a finite capacitance which is charged or discharged. The current outputted by the transistors 5 and 12 varies rapidly in time and develops a voltage (i.e. a large Ldi/dt) across the output lead inductances (i.e., bonding wire and packaging inductances) which in turn leads to noise, e.g., spikes, on the power supply bus. This may result in one or more erroneous logic values being outputted from the output buffer circuit 20.
This problem is compounded if several parallel output buffer circuits are provided. Typically, these output buffer circuits are each connected to the power supply via the same power supply bus. When operating in parallel, the noise produced by each output buffer connected to the same power supply bus tends to couple to other output buffers. Thus, noise produced by an abrupt change in the logic value outputted from one output buffer circuit can cause an erroneous logic value to be outputted from another output buffer circuit connected to the same power supply bus.
In addition to the noise problem, the output buffer circuit may be damaged if the output pad is short circuited. A huge current may be developed if the output pad is short circuited to a voltage supply or another output driver circuit when the transistor 5 or 12 begins supplying current during a transition of the output pad voltage. This huge current can cause catastrophic damage to the integrated circuit.
A number of prior art solutions have been proposed for reducing the effect of noise on the voltage outputted by the output buffer circuit. FIG. 2 shows a first prior art output buffer circuit 240 disclosed in U.S. Pat. No. 5,168,176 (Wanlass). In FIG. 2, lead inductances are shown as inductors L201 (connected to the negative reference voltage supply, e.g., ground), L202 (connected to the positive reference voltage supply V.sub.dd), and L203 (connected to an output pad 210). The capacitance of the output pad 210 is shown as C.sub.L. The Wanlass output buffer circuit 240 is provided with a P-MOS transistor P201 for supplying a current to the output pad 210 at a high pad voltage. A first N-MOS transistor N201 is provided for supplying a high sink current to the output pad 210 at a low pad voltage when a high input logic signal voltage appears on the input 220. A second N-MOS transistor N202 is provided in parallel to the first N-MOS transistor N201 for supplying a smaller sink current to the output pad 210 at a low pad voltage when a high input logic signal voltage appears on the input 220. A circuit is provided, such as the Schottky diode SD201, for controlling the flow of current in the first transistor N201. The Schottky diode SD201 permits the transistor N201 to supply its current to the output pad 210 only when the output pad voltage exceeds a certain threshold voltage above the low pad voltage. Thus, the Schottky diode SD201 permits the transistor N201 to supply its large sinking current initially to pull the output pad 210 from an initial high voltage to the threshold voltage. Thereafter, the Schottky diode SD201 blocks the transistor N201 from conducting any current unless the output pad voltage exceeds the threshold voltage. For example, if noise raises the output pad 210 voltage above the threshold, the Schottky diode SD201 once again permits the transistor N201 to supply its current to pull the output pad 210 voltage low.
The Wanlass output buffer circuit 240 does not provide short circuit protection. This is because both transistors N201 and N202 supply a current if the output pad 210 is at a high voltage. Thus, if a positive voltage supply were connected to the output pad 210 when a high voltage appears on the input 220, the transistor N201 may generate an extremely high current which can cause catastrophic damage to the integrated circuit containing the output buffer 240.
FIG. 3 shows another output buffer circuit 700 depicted in U.S. patent application Ser. No. 734,752, entitled "Apparatus and Method to Prevent the Disturbance of a Quiescent Output Buffer Caused by a Ground Bounce or by Power Bounce Induced by Neighboring Active Output Buffers" filed Jul. 23, 1991 for Frank Wanlass. This application is assigned to the assignee hereof. In FIG. 3, lead inductances are labeled L and the output capacitance is labeled C.sub.L. The output buffer circuit 700 includes a P-channel circuit 701 for outputting a high pad voltage at the output pad 790 in response to receiving a logic low input logic signal voltage on the input 780. The P-channel circuit 701 includes the inverters 708 and 758, NOR gate 756, Schottky diode 706, and transistors 744 and 748, which are connected to noisy and quiet voltage supplies, respectively. The output buffer circuit 700 also includes an N-channel circuit 702 for outputting a low pad voltage at the output pad 790 in response to receiving a logic high input signal voltage on the input 780. The N-channel circuit 702 includes the inverters 709 and 754, the NAND gate 752, the Schottky diode 707 and the transistors 742 and 746. The transistors 742 is connected to a noisy ground. The transistor 746 is connected to a quiet ground. Both transistors 742 and 746 are capable of sinking a high current (e.g., 100 mA).
When a high voltage is inputted on the input 780, initially the transistor 746 is off and the transistor 742 is turned on by a control circuit such as the Schottky diode 707. The transistor 742 supplies a current to the output pad 790. This supplied current discharges the output capacitance C.sub.L to the noisy ground. When the voltage of the output pad 790 drops to a certain level, the Schottky diode 707 turns the transistor 742 off. Furthermore, when the voltage of the output pad 790 drops to this level, the inverters 709 and 754 and the NAND gate 752 turn the transistor 746 on. The transistor 746 then supplies a current to the output pad 790.
The circuit 700 does not provide any short circuit protection as only large transistors are used. Thus, if the output pad 790 is short circuited to a positive voltage supply when a high voltage appears on the input 790, the transistor 742 may supply an extremely high current which can damage the integrated circuit. Furthermore, the circuit 700 requires electrically isolated noisy and quiet grounds and voltage supplies. An additional consequence of providing isolated quiet and noisy ground and power supply nodes is that the transistors 742 and 746 ideally should not be on at the same time. If the transistors 742 and 746 were both on at the same time, noise would couple from the noisy power supply and ground nodes to the quiet power supply and ground nodes.
FIG. 4 depicts a prior art output buffer circuit 340 disclosed in U.S. Pat. No. 5,036,222 (Davis). In FIG. 4, an output enable signal is received at a serial connection of the inverters 318 and 320. The output of the inverter 320 is fed to a NAND gate 315 via an inverter 322 and to a NOR gate 316. An inputted logic signal voltage is received at the input Vin of a serial connection of the inverters 312 and 314. The output of the inverter 314 is inputted to the NAND gate 315 and the NOR gate 316. The output of the NOR gate 316 forms the N-channel input and the output of the NAND gate 315 forms the P-channel input.
The P-channel input is fed to a P-channel circuit 351 including the transistors P301, P302, P303, and N304 and the inverter 344. The P-channel circuit 351 outputs a current to the output pad 353 at a high output pad voltage Vout when a high input logic signal voltage is inputted at Vin. Likewise the N-channel input is fed to an N-channel circuit 352 including the transistors N301, N302, N303, and P304 and the inverter 342. The N-channel circuit 352 outputs a high current to the output pad 353 at a low output pad voltage Vout when a low input logic signal voltage is inputted at Vin.
In the N-channel circuit 352, the transistor N301 supplies the output pad with a smaller current than the transistor N303. When the voltage to be outputted at Vout from the output buffer circuit 340 is to be changed from high to low, the transistor N303 is initially off. The transistor N301 turns on and discharges the output capacitance of the output pad 353 by supplying a small sinking current. This causes the output pad voltage Vout to drop. When the output pad voltage Vout falls below the turn on voltage of the transistor P304, the transistor P304 turns on thereby turning on the transistor N303. The transistor N303 then supplies a current to the output pad Vout. The P-channel circuit 351 operates in a symmetrical fashion.
The disadvantage of the circuit 340 is that no short circuit protection is provided once the transistor N303 turns on. When the voltage at the output pad Vout drops to a certain level, the transistor P304 turns on and supplies a current which charges up the gate of the transistor N303. If the output pad Vout were to be subsequently short circuited to a positive voltage supply, the transistor P304 would turn off. However, the transistor N303 would remain on because of the charge stored at its gate. Thus, an extremely high current could flow through the transistor N303 which can damage the integrated circuit containing the output buffer circuit 340.
FIG. 5 shows yet another prior art output buffer circuit 440 disclosed in U.S. Pat. 4,777,389 (Wu). In FIG. 5, a voltage inputted at D is inverted by an inverter 416. The output of the inverter 416 is fed to a P-channel circuit 491. The P-channel circuit 491 outputs a high current to an output pad A at a high output pad voltage when a high input logic signal voltage is inputted at D. The P-channel circuit 491 includes inverters 418 and 420, NAND gate 413, NOR gate 412 and transistors N401, N404 and N405.
The output of the inverter 416 of FIG. 5 is also fed to an N-channel circuit 492. The N-channel circuit 492 outputs a high current to the output pad A at a low output pad voltage when a low input logic signal voltage is inputted at D. The N-channel circuit 492 includes the inverter 422, the NAND gate 417, the NOR gates 414 and 415 and the transistors N403, N406, N407, and N408.
In FIG. 5, both of the transistors N403 and N408 are for supplying the output A with a high current at a low pad voltage. When a low voltage appears at the input D, the NOR gate 414 outputs a high voltage after a delay caused by the inverters 416 and 422 and the NOR gate 414. Meanwhile, the combination of the initially high voltage of the output pad A and the high voltage outputted from the inverter 416 causes the AND gate 417 to turn on transistor N407. The output of the transistor N407 (initially) and the output of the NOR gate 414 (after a delay) cause the voltage at the gate of transistor N403 to rise slowly thereby slowly turning on the transistor N403. The transistor N403, in turn, slowly supplies current to the output pad A which causes the voltage at the output pad A to drop. When the voltage at the output pad A falls below a certain voltage, the NOR gate 415 abruptly changes from outputting a low voltage to outputting a high voltage. The high voltage outputted from the NOR gate 415 abruptly turns on the transistor N408 which supplies current to the output pad A.
A principle disadvantage of the output buffer circuit 440 of FIG. 5 lies in its complexity. In order to reduce noise on the output, four transistors and five logic circuits must be provided in the N-channel circuit. Thus, a large area is required for outputting each bit from the integrated circuit containing the circuit 440. Furthermore, some of the logic circuits used to control the transistors N403 and N408, i.e.,the two logic circuits 414 and 415, have more than two inputs. This makes it difficult to add additional modules with additional current supply elements and associated control circuitry.
FIG. 6 shows another prior art output buffer circuit 500 disclosed in U.S. Pat. No. 4,731,553 (Van Lehn). In FIG. 6, a P-channel circuit 591 is provided for supplying a high current to the output pad 510 at a high pad voltage in response to a low input logic signal voltage appearing on the input 505. The P-channel circuit 591 includes the NOR gates 502 and 518, the inverter 520 and the transistors 522 and 508. The inverter 520 includes two transistors 521a and 521b. An N-channel circuit 592 is also provided for supplying a high current to the output pad 510 at a low pad voltage in response to a high input logic signal voltage appearing on the input 505. The N-channel circuit 592 includes the inverters 504, 540, and 512, the NAND gates 528 and 506, the inverters 530 and 544 the resistors 516 and 526 and the transistors 514, 532, and 536. The inverter 530 includes the transistors 531a and 531b and the inverter 538 includes the transistors 542 and 544. The inverters 538 and 540, the transistors 534 and 536 and the NAND gate 506 form a switch circuit 590. The inverter 530 forms a delay circuit which turns on the transistor 532 in response to receiving a high voltage on the input 505 after a particular delay.
In FIG. 6, when a high voltage appears on the input 505, the transistor 514 connected to a noisy ground (DVss) initially turns on. This causes the voltage of the output pad 510 to drop. The switch circuit 590 turns off the transistor 514 when the voltage of the output 590 drops to a certain voltage level. In addition, in response to the high voltage appearing on the input 505, the delay circuit 530 turns on the transistor 532 which is connected to a quiet ground (CVss). The delay circuit 530 is designed to delay the turn on of the transistor 532 until the transistor 514 is off.
The biggest disadvantage of the output buffer circuit 500 is that no short circuit protection is provided. This is because both transistors 514 and 532 always turns on in response to the appropriate voltage appearing on the input 505 no matter how large the output pad voltage becomes. Thus, if the output pad 510 is short circuited to a positive voltage supply when a high voltage appears on the input 505, the transistors 514 and 532 may generate an extremely high current. In addition to this disadvantage, isolated noisy and quiet grounds must be provided in the output buffer circuit 500. As an additional consequence of providing separate noisy and quiet grounds, the transistors 532 and 514 cannot be on at the same time. The reason for this is that noise would otherwise couple between the noisy ground and the quiet ground.
FIG. 7 shows a further prior art output buffer circuit 602 disclosed in U.S. Pat. No. 4,928,023 (Marshall). An inputted logic signal voltage and an enable signal are received at a NAND gate 610. The inputted enable signal and output of the NAND gate 610 are received at a NAND gate 616. A P-channel circuit 691 is provided for supplying a high current to an output pad 615 at a high pad voltage value when a high input logic signal voltage appears on the input 605. The P-channel circuit 691 includes the inverter 612 and transistor 614. An N-channel circuit 692 is also provided for supplying a high current to the output pad 615 at a low pad voltage when a low input logic signal voltage appears on the input 605. Thus, the output buffer circuit 602 of F16 7 is non-inverting. The N-channel circuit 692 includes the inverter 618, the transistors 632 and 628, the drive circuit 630 and the switch circuit 640. The drive circuit 630 includes the transistors 620, 622, 624 and 626. The switch circuit 640 includes the transistors 634, 636, 638 and 642. The transistor 628 supplies a larger current than the transistor 632. Furthermore, the transistor 628 is connected to a noisy ground DVss and the transistor 632 is connected to a quiet ground CVss, which noisy and quiet grounds DVss and CVss are electrically isolated from each other.
When a low input logic signal voltage is received at the input 605, the drive circuit 630 causes the transistor 628 to turn on. The transistor 628 supplies a high current to the output pad 615 to discharge the output pad 615 to the noisy ground node DVss. This in turn causes the voltage of the output pad 615 to drop. As the voltage of the output pad 615 drops, the drive circuit 630 turns off the transistor 628. Furthermore, the drive circuit 630 causes the switch circuit 640 to turn on the transistor 632. The transistor 632 then supplies a small current at a low voltage to the output pad 615.
The Marshall output buffer 602 does not provide any short circuit protection as the high current supply transistor 628 is turned on initially to supply a high current to the output pad 615. Thus, if a positive voltage supply is connected to the output pad 615 while the transistor 628 is on, the transistor 628 may generate a huge current that can damage the integrated circuit. In addition, isolated noisy and quiet grounds must be provided in the output buffer circuit 602. As an additional consequence of requiring isolated noisy and quiet grounds, the transistors 628 and 632 cannot both be on at the same time.
In short, the above-described prior art output buffers are disadvantageous because they do not offer adequate short circuit protection. As mentioned above, if the output buffer is short circuited to a voltage supply or another output driver, the transistors of a prior art output buffer may supply an extremely high current. This can result in catastrophic damage to the integrated circuit. In addition, the above-described prior art output buffer circuits are extremely complex, i.e., they require complex control circuitry for controlling the elements which supply current for charging or discharging the output pad.
It is therefore an object of the present invention to provide an output buffer circuit which overcomes the disadvantages of the prior art.